As known in the art, through-substrate vias (referred to herein as TSVs), which are commonly referred to as through-silicon vias, are vertical electrical connections that extend from one of the metal interconnect levels formed on the top surface of a wafer or IC die (e.g., one of the metal interconnect levels) to a location accessible from the bottom of the IC die. As a result, the TSV comprising device can be bonded face-up and utilize vertical electrical paths to couple from the bottom of the IC die to workpiece electrical connectors (e.g., attach or “land” pads) on other IC devices (e.g., on a die, wafer) or to mount onto a package substrate. The vertical electrical paths are significantly shortened relative to conventional wire bonding technology, generally leading to significantly faster device operation. TSVs generally include TSV tips that protrude a distance from the bottom of the IC die, such as a distance from 5 to 30 μms.
Pillars are another type of protruding conductive features used to join electronic devices. Pillars protrude from the top surface of the IC die and typically have a length from 10 to 50 μms. ICs having pillars are assembled in a flip chip configuration to attach pads on a workpiece.
Due to process variations as well as warpage induced bow, the length of the protruding bonding features (e.g., TSV tips, pillars or coined studs) across the IC die can vary significantly, such as having a range between 5 to 15 μm long. Non-uniformity in the length of the protruding bonding features across an IC die is conventionally addressed by using a solder thickness on the tip of the bonding features that is sufficient to compensate for the height difference (e.g., 15 μm thick solder for a length variation range of 10 μm). However, the solder compensating approach can lead to bonding problems such as variable solder amounts between the protruding bonding features (e.g., TSVs or pillars) and the electrical connectors (e.g., attach pads) on the workpiece surface. In regions where the solder is relatively thick, following bonding processing unreacted solder can remain which leads to variable electromigration (EM) performance, yield loss due to poor bonding (e.g., high resistance joints), and/or solder induced short circuits. Moreover, bond alignment inaccuracy can lead to variable bond integrity.
Some known solutions used to reduce the effects from non-uniformity in the length of the protruding bonding features include the use of a redistribution layer (RDL) pad over the protruding bonding features. The RDL approach adds extra wafer-level processing steps which results in extra cost, and has alignment complexities associated with backside wafer processing. Another known solution comprises chemical-mechanical planarization/chemical-mechanical polishing (CMP) of the bottom of the wafer to achieve improved co-planarity of the protruding bonding features. The CMP method adds an extra step and results in extra cost, and can damage the protruding bonding features, such as smearing of the metal filler or cracking of the dielectric liner in the case of TSVs.